Our Publications in Research Conferences Around the World

  • Vandana Thind, Bishwajeet Pandey, D M Akbar Hussain, “Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA”, IEEE PES Power Africa Conference, Livingstone, Zambia, 21-25 June, 2016. (Accepted)
  • Harkinder Kaur, Harsh Sohal and Jaiteg Singh, "Design and performance analysis of UART using Altera Quartus-II and Xilinx ISE 14.2",The International Conference on Communication Systems and Network Technologies (CSNT-2016), 05-07 March, 2016.
  • Shivangni Singh, Neha Agrawal, Madhavika Agarwal, Anjan Kumar and Bishwajeet Pandey, “Simulation And Verification Of Voltage And Capacitance Scalable 32-bit Wi-Fi ah Channel Enable ALU Design on 40nm FPGA”, Seventh IEEE International Conference on Computational Intelligence and Communication Networks (CICN), 12-14 Dec 2015, Jabalpur, India.
  • Rashmi Sharma, Navya Bhasin, Bishwajeet Pandey, Mohammad Abdullah, Bhagwan Das and Vaashu Sharma, “Replicating an Energy Efficient Human Brain Using 40nm FPGA Technology”, Seventh IEEE International Conference on Computational Intelligence and Communication Networks (CICN), 12-14 Dec 2015, Jabalpur, India.
  • Aniruddh Khanna, Mansee Jain, Tanesh Kumar, Deepa Singh, Bishwajeet Pandey, Vikas Jha “Anatomy and Utilities of an Artificial Intelligence Conversational Entity”, Seventh IEEE International Conference on Computational Intelligence and Communication Networks (CICN), 12-14 Dec 2015, Jabalpur, India.
  • Shivani Madhok, Simran Chabra, D M Akbar Hussain, Bhagwan Das, M F L Abdullah, Bishwajeet Pandey, “Energy Efficient Receiver and Transmitter Design for Free Space Optical Communication”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Shivani Madhok, Ritika Mahajan, D M Akbar Hussain, Bhagwan Das, M F L Abdullah, Bishwajeet Pandey, “Internet Of Things(IoTs) Enable Decoder Design For Wireless Sensor Network”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Arushi Aggarwal, Bishwajeet Pandey, Sweety Dabbas, Achal Agarwal, Siddharth Saurabh, “LVCMOS Based Low Power Thermal Aware Energy Proficient Vedic Multiplier Design on Different FPGA's”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Arushi Aggarwal, Bishwajeet Pandey, Sweety Dabbas, Achal Agarwal, Siddharth Saurabh “Stub Series Terminal Logic Based Low Power Thermal Aware Vedic Multiplier Design On 40-nm FPGA”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Vandana Thind, Sujeet Pandey, D M Akbar Hussain, Bhagwan Das, M F L Abdullah, Bishwajeet Pandey, “Timing Constraints Based High Performance Des Design And Implementation On 28nm FPGA”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Rashmi Sharma, Bishwajeet Pandey, Vikas Jha, Siddharth Saurabh, Sweety Dabas, “Input Output Standard Based Energy Efficient UART Design on 90nm FPGA”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Ketan Sethi, Puneet Tomar, Bishwajeet Pandey, “Environment Friendly Air Conditioner Design Using Cooling Pot and Solar Panel”, Springer Index Special session on Green Computing in 50th Golden Jubilee Annual Convention of Computer Society of India (CSI-2015) on Digital Life, 02nd – 05th December, 2015, Delhi, India.
  • Madhavika Agarwal, Shivangni Singh Neha Agrawal, Anjan Kumar and Bishwajeet Pandey, “Frequency Scaling Based Thermally Tolerable Wi-Fi Enable 32-bit ALU Design on 90nm FPGA”, International Conference on Communication Control and Intelligent System (CCIS-2015), GLA University, Mathura, India 07-08 November 2015
  • Neha Agrawal, Madhavika Agarwal, Shivangni Singh, Anjan Kumar and Bishwajeet Pandey, “Different I/O Standard Based Wi-Fi Enable 32-bit ALU Design on 90nm FPGA”, International Conference on Communication Control and Intelligent System (CCIS-2015), GLA University, Mathura, India, 07-08 November 2015
  • Kanika Garg, Aditi Moudgil, Bhagwan Das, M F L Abdullah, Bishwajeet Pandey, D M Akbar Hussain, “GTL Based Internet of Things Enable Processor Specific RAM Design on 65nm FPGA”, IEEE 57th International Symposium ELMAR-2015. 28-30 September 2015, Zadar, Croatia: the oldest conference in Europe.
  • Kartik Kalia, Shivani Malhotra, Khyati Nanda, Bishwajeet Pandey “GTL Based Wireless Sensor Specific Energy Efficient ALU Design on 65nm FPGA”, IEEE International Conference on Signal Processing, Computing and Control (ISPCC), Solan, India, 24-26 September 2015.
  • Shivani Madhok, Bishwajeet Pandey, D M Akbar Hussain, Tushar Madhok, Tanesh Kumar and Kartik Kalia, “HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA”, Scopus International conference on Green Computing and Engineering Technology 2015 (ICGCET'15), 25-26 July 2015, Dubai, UAE. http://www.sersc.org/journals/IJCA/vol8_no8/5.pdf
  • Deepa Singh, Kanika Garg, Ravneet Singh, Hashmatullah Noori, Bishwajeet Pandey and Kartik Kalia, “Thermal aware Internet of Things Enable Energy Efficient Encoder Design on FPGA”, Scopus International conference on Green Computing and Engineering Technology 2015 (ICGCET'15), 25-26 July 2015, Dubai, UAE. http://www.sersc.org/journals/IJSIA/vol9_no6_2015/26.pdf
  • Anirudh Khanna, Bishwajeet Pandey, Bhale Pradeepkumar, Kartik Kalia, Kushagra Vashishta and Teerath Das “A Study of Today’s A.I. through Chatbots and a Rediscovery of Machine Intelligence”, Scopus International conference on Green Computing and Engineering Technology 2015 (ICGCET'15), 25-26 July 2015, Dubai, UAE. http://www.sersc.org/journals/IJUNESST/vol8_no7/28.pdf
  • Sumita Nagah, Bishwajeet Pandey, Ravinder Kaur, Mahbub-E- Noor, Md. Saifur Rahman and Kartik Kalia, “I/O Standards Based on Green Communication Using Fibonacci Generator Design on FPGA”, Scopus International conference on Green Computing and Engineering Technology 2015 (ICGCET'15), 25-26 July 2015, Dubai, UAE. http://www.sersc.org/journals/IJCA/vol8_no8/13.pdf
  • Vandana Thind, Bishwajeet Pandey, Simran Kaur Sandhu, Sumit Sharma and Tamanna Walia, "SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA”, Scopus International conference on Green Computing and Engineering Technology 2015 (ICGCET'15), 25-26 July 2015, Dubai, UAE. http://www.sersc.org/journals/IJSIA/vol9_no7_2015/23.pdf
  • Kartik Kalia, Bishwajeet Pandey, Amanpreet Kaur, Khyati Nanda, Shivani Malhotra, D.M.A Hussain, “Pseudo Open Drain IO Standard Based Energy Efficient Solar Charge Sensor Design on 20nm FPGA”, 11th IEEE International Conference on Power Electronics and Drive Systems (PEDS 2015), Sydney, Australia, 9 – 12 June 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7203530
  • M.F.L Abdullah, Bhagwan Das, M S N Shahida, Bishwajeet Pandey, et al. “Energy-Efficient Pseudo Noise Generator Based Optical Transmitter for Ethernet(IEEE 802.3az)”, IEEE/Scopus Int. Conf. on Computer, Communication, and Control Technology (I4CT’15), 21 – 23 April 2015, Kuching, Sarawak, Malaysia. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7219554
  • Sakshi Aggarwal, Gaurav Verma, Amanpreet Kaur, Bishwajeet Pandey, Sunny Singh and Rakesh Kumar, “Green ECG Machine Design Using Different Logic Families”, IEEE International Conference on Communication Systems and Network Technologies (CSNT), Gwalior, India, April 2015. http://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?arnumber=7280036
  • Tukur Gupta, Gaurav Verma, Amanpreet Kaur, Bishwajeet Pandey, Amandeep Singh and Tarandeep Kaur, “Energy Efficient Counter Design Using Voltage Scaling On FPGA”, IEEE International Conference on Communication Systems and Network Technologies (CSNT), Gwalior, India, April 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7280033
  • Shaina Verma, Divya Gaba, Bishwajeet Pandey, “GTL IO Standards Based WLAN Specific Low Power ALU Design on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharti Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100495
  • Kartik Kalia, Khyati Nanda, Shivani Malhotra, Bishwajeet Pandey, “HSTL Based Low Power Thermal Aware Adder Design on 65nm FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharti Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100496
  • Gaurav Verma, Aditi Moudgil, Kanika Garg, Bishwajeet Pandey,“Thermal and Power Aware Internet of Things Enable RAM Design on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharti Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100506
  • Love Kumar, Tanesh Kumar, M. F. Alam, S.H.A. Musavi, and Bishwajeet Pandey, “Simulation of High Performance Energy Efficient Human Brain on 28nm FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharti Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?tp=&arnumber=7100508
  • Kavita Goswami, and Bishwajeet Pandey, “Voltage Scaling Based Low Power High Performance Vedic Multiplier Design on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100504
  • Ravinder Kaur, Jagdish Kumar, Sumi Nagah, Kavita Goswami, Bishwajeet Pandey, “Different IO Standard Based Low Power Memory Design and Implementation on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100498
  • Kavita Goswami, Bishwajeet Pandey, “Reduction of I/O Power using Energy Efficient HSTL I/O Standard in Vedic Multiplier on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100501
  • Sumita Nagah, Tanesh Kumar, Bishwajeet Pandey, Ravinder Kaur, DM Akbar Hussain, Bhawani Shankar Chowdhry, "SSTL IO Standard Based Green Communication Using Fibonacci Generator Design on Ultra Scale FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100502
  • Amanpreet Kaur, Gurpreet Singh, Bishwajeet Pandey, Furqan Fazili, “Thermal Aware Energy Efficient Gurumukhi Unicode Reader for Natural Language Processing”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100503
  • Amanpreet Kaur, Gurpreet Singh, Bishwajeet Pandey, Furqan Fazili, “Capacitance Scaling Based Green Gurumukhi Unicode Reader Design for Natural Language Processing”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, India, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100494
  • Shivani Madhok, Amanpreet Kaur, Bishwajeet Pandey “Different IO Standard Based Energy Efficient Decoder Design For 64-bit Processor Architecture”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7100559
  • Meenakshi Bansal, Neha Bansal, Rishita Saini, Lakshay Kalra and Bishwajeet Pandey, “HSTL I/O Standard Based Environment Friendly Energy Efficient ROM Design on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, 11-13 March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100560
  • Lakshay Kalra, Neha Bansal, Rishita Saini, Meenakshi Bansal, Bishwajeet Pandey “LVCMOS I/O Standard Based Environment Friendly Low Power ROM Design on FPGA”, IEEE International Conference on “Computing for Sustainable Global Development (INDIACOM), Bharati Vidyapeeth, Delhi, 11-13 March 2015. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7100561
  • Bhagwan Das, M.F.L Abdullah, Bishwajeet Pandey, et al. “Temperature Control of Pseudo Noise Generator Based Optical Transmitter using Airflow and Heat Sink Profile at High Speed Transceiver Logic IO Standard”, Int. Conf. on Sensors, Materials and Manufacturing (ICSMM), Ho-Chi-Minh, Vietnam, February 2015. http://www.joace.org/uploadfile/2015/0529/20150529042946338.pdf
  • Shaina Verma, Divya Gaba, Bishwajeet Pandey, “HSUL Based 802.11 WLAN Channel Specific Energy Efficient ALU Design on FPGA”, 2nd International Conference on Signal Processing and Integrated Networks (SPIN), pp. 860-864, Amity University, Noida, India, February 2015. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7095167
  • Bishwajeet Pandey, Gurpreet Singh, Umar Farooq and Rashid Siddique Parhyar, “Simulation of HSTL IO Standard Based Energy Efficient Punjabi Unicode Reader on FPGA”, IEEE International Conference on Open Source Systems and Technologies (ICOSST), December, 2014, Lahore, Pakistan. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=702932116.
  • Kavita Goswami, Bishwajeet Pandey, “Energy Efficient Vedic Multiplier Design Using LVCMOS and HSTL IO Standard”, IEEE 9th International Conference on Industrial and Information Systems (ICIIS), IIIT Gwalior, India 15-17 December, 2014. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7036602
  • Sunny Singh, Amanpreet Kaur, and Bishwajeet Pandey, “Energy Efficient Flip Flop Design Using Voltage Scaling On FPGA”, IEEE Sixth India International Conference on Power Electronics (IICPE), NIT Kurukshetra, India 8-10 December, 2014. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=7115855
  • Anu Singla, Amanpreet Kaur, and Bishwajeet Pandey, “LVCMOS Based Energy Efficient Solar Charge Sensor Design on FPGA”, IEEE Sixth India International Conference on Power Electronics (IICPE), NIT Kurukshetra, 8-10 December, 2014. http://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?reload=true&tp=&arnumber=7115800
  • Meenakshi Bansal, Neha Bansal, Rishita Saini, Bishwajeet Pandey, Lakshay Kalra, Dil Hussain, “SSTL I/O Standard Based Environment Friendly Energy Efficient ROM Design on FPGA”, IEEE 3rd International Symposium on Environment-Friendly Energies and Applications (EFEA), November 2014, Paris, France. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7059947.
  • Bishwajeet Pandey, Gurpreet Singh, “Simulation of CMOS IO Standard Based Energy Efficient Gurmukhi Unicode Reader on FPGA”, IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN), Udaipur, India, November, 2014. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7065613
  • Kavita Goswami, Bishwajeet Pandey, “LVCMOS Based Thermal Aware Energy Efficient Vedic Multiplier Design on FPGA”, IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN), Udaipur, India, November, 2014. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7065614
  • Rishita Saini, Meenakshi Bansal, Neha Bansal and Lakshay Kalra, Bishwajeet Pandey, “Low Power High Performance ROM Design on FPGA using LVDCI I/O Standard”, IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN), Udaipur, India, November, 2014. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7065617
  • Sunny Singh, Abhishek Jain and Amanpreet Kaur, Bishwajeet Pandey, “Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA”, IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN), Udaipur, India, 14-16 November, 2014. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7065618
  • Karandeep Kaur, Bishwajeet Pandey, Jagdish Kumar, Abhishek Jain, Parminder Kaur, “Internet of Things Enabled Energy Efficient Green Communication on FPGA”, IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN), Udaipur, India, November, 2014. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7065620
  • Kavita Goswami, Bishwajeet Pandey, Abhishek Jain, Deepa Singh, “Low Voltage Digitally Controlled Impedance Based Energy Efficient Vedic Multiplier Design on 28nm FPGA”, IEEE 6th International Conference on Computational Intelligence and Communication Networks (CICN), Udaipur, India, November, 2014. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7065621
  • Tanesh Kumar, Teerath Das, Bishwajeet Pandey, Atiqur Rahman, Amanpreet Kaur, DM Akbar Hussain, "LVTTL Based Energy Efficient Watermark Generator Design and Implementation on FPGA", IEEE International Conference on ICT Convergence 2014, 22-24 October, Busan, Korea, http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6983240
  • Neha Bansal, Meenakshi Bansal, Lakshay Kalra, Bishwajeet Pandey and Rishita Saini, “Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA”, Scopus 4th International Conference on Advanced Materials and Engineering Materials (ICAMEM), 19-20 October 2014, Hong Kong. http://www.scientific.net/AMR.1082.467
  • Neha Bansal, Meenakshi Bansal, Lakshay Kalra, Bishwajeet Pandey and Rishita Saini, “FPGA Based Low Power ROM Design Using Capacitance Scaling”, Scopus 4th International Conference on Advanced Materials and Engineering Materials (ICAMEM), 19-20 October 2014, Hong Kong. http://www.scientific.net/AMR.1082.471
  • Tanesh Kumar, Teerath Das, Bishwajeet Pandey, Dil Muhammad Akbar Hussain, "IO Standard Based Thermal/Energy Efficient Green Communication For Wi-Fi Protected Access on FPGA", 6th IEEE International Congress on Ultra-Modern Telecommunications and Control systems and Workshops, St. Petersburg, Russia, 06-08 October 2014, http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7002085
  • Teerath Das, Bishwajeet Pandey, Tanesh Kumar, Parkash Kumar and Love Kumar “Simulation of SSTL IO Standard Based Power Optimized Parallel Integrator Design on FPGA”, IEEE International Conference on Robotics & Emerging Allied Technologies in Engineering (iCREATE), April 2014, Islamabad, Pakistan http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828328
  • Tanesh Kumar, Bishwajeet Pandey, Teerath Das, Sweety Dabas and Parkash Kumar “Simulation of Voltage Based Efficient Fire Sensor on FPGA Using SSTL IO Standards”, IEEE International Conference on Robotics & Emerging Allied Technologies in Engineering (iCREATE), April 2014, Islamabad, Pakistan. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828332
  • Tanesh Kumar, Madhu Maya Limbu, Akash Kumar, Bishwajeet Pandey and Teerath Das “Simulation of HSTL IO Standard Based Energy Efficient Frame Buffer For Digital Image Processor”, IEEE International Conference on Robotics & Emerging Allied Technologies in Engineering (iCREATE), April 2014, Islamabad, Pakistan. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828331
  • Prabhat Singh, Bishwajeet Pandey, Tanesh Kumar, Teerath Das, “I/O Standard Based Power Optimized Processor Register Design on Ultra Scale FPGA”, IEEE International Conference on “Computing for Sustainable Global Development(INDIACOM), Delhi, India, pp. 172-177, March, 2014. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06828123
  • Bhavani Shankar Chowdhry, Bishwajeet Pandey, Tanesh Kumar, Pardeep Kumar, and K R Dayo, "LVTTL Based High Performance Energy Efficient 64-bit ALU Design on FPGA", International Conference on Modern Communication & Computing Technologies (MCCT'14), Nawabshah, Pakistan, February, 2014. http://mcct.quest.edu.pk/full_papers/paper_42.pdf
  • Bhavani Shankar Chowdhry, Bishwajeet Pandey, Tanesh Kumar, Pardeep Kumar, and K R Dayo, "Thermal Aware Energy Efficient ALU Design on Ultra Scale FPGA", International Conference on Modern Communication & Computing Technologies (MCCT'14)- Nawabshah, Pakistan, February, 2014, http://mcct.quest.edu.pk/full_papers/paper_41.pdf
  • Bishwajeet Pandey, Jyotsana Yadav, Pooja Saigal, Tanesh Kumar, Teerath Das, Kumar Satyam “Reliable ALU Design with Optimized Voltage and Implementation on 28nm FPGA”, IEEE International Conference on Reliability Optimization & Information Technology (ICROIT), Faridabad, India, February, 2014. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6798381
  • Bishwajeet Pandey, Tanesh Kumar, Teerath Das, Rahul Yadav, Om Jee Pandey, "Capacitance Scaling Based Energy Efficient FIR Filter For Digital Signal Processing", IEEE International Conference on Reliability Optimization & Information Technology (ICROIT), Faridabad, India, February, 2014. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6798382
  • Sweety Dabbas, Bishwajeet Pandey, Tanesh Kumar, and Teerath Das, "Design of Power Optimized Memory Circuit Using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array", IEEE International Conference on Reliability Optimization & Information Technology (ICROIT), Faridabad, India, February, 2014. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6798384
  • Ashraf Uddin, Sumit Banshal, Md Atiqur Rahman, Teerath Das, Tanesh Kumar, Bishwajeet Pandey, "Thermal Aware Energy Efficient Bengali Unicode Reader in Text Analysis", IEEE International Conference on Reliability Optimization & Information Technology (ICROIT), Faridabad Faridabad, India, February, 2014. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6798356
  • Prabhat Singh, Om Jee Pandey, Bishwajeet Pandey, Teerath Das, Tanesh Kumar, “Output Load Capacitance Based Low Power Implementation of UART on FPGA”, IEEE International Conference on Computer Communication and Informatics (ICCCI) at Coimbatore, India, January 2014. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6921826
  • Sumit Banshal, Bishwajeet Pandey, S J Bendra “Capacitance Scaling Aware Power Optimized Register Design And Implementation on 28nm FPGA”, IEEE International Conference on Computer Communication and Informatics (ICCCI) at Coimbatore, India, January 2014. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6921838
  • S. M. Mohaiminul Islam, Bishwajeet Pandey, Shashank Jaiswal, Md. Mahbub-E-Noor and Shah Md. Tanvir Siddiquee, "Simulation of Voltage Scaling Aware Mobile Battery Charge Controller Sensor on FPGA", 3rd International Conference on Advanced Materials and Engineering Material(ICAMEMs), 14-15 December 2013, Singapore, http://www.ttp.net/978-3-03835-025-5/17.html
  • B. S. Chowdhry, Bishwajeet Pandey, Tanesh Kumar, Teerath Das, Sujit Thakur, "Frequency, Voltage and Temperature Sensor Design for Fire Detection in VLSI Circuit on FPGA", Springer International Multitopic Conference (IMTIC'13), December, 2013, Mehran University, Sindh, Pakistan, http://link.springer.com/chapter/10.1007/978-3-319-10987-9_12
  • Pooja Saigal, Bishwajeet Pandey, Ekta Walia “Design of Frame Buffer for 1 THz Energy Efficient Digital Image Processor based on HSLVDCI I/O Standard in FPGA”, IEEE International Conference on Signal Processing and Communication(ICSC) at JIIT Noida, India, December 2013, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6719799.
  • Bishwajeet Pandey, Jyotsana Yadav, Manisha Pattanaik “IO Standard Based Energy Efficient ALU Design and Implementation on 28nm FPGA”, 10th IEEE India Conference (INDICON) 2013, IIT Bombay, India, December 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6725996
  • Tanesh Kumar, Bishwajeet Pandey, and Teerath Das, " LVCMOS I/O Standard And Drive Strength Based Green Design on Ultra Scale FPGA", IEEE International conference on Green Computing, Communication and Conservation of Energy(ICGCE), Chennai, India, December, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6823411
  • Tanesh Kumar, Bishwajeet Pandey, and Teerath Das, "Digitally Controlled Impedance Based Green Design on Ultra Scale FPGA", IEEE International conference on Green Computing, Communication and Conservation of Energy(ICGCE), Chennai, India, December, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06731996
  • Tanesh Kumar, Bishwajeet Pandey, and Teerath Das, " Voltage Scaling Based Green Design on Ultra Scale FGPA", IEEE International conference on Green Computing, Communication and Conservation of Energy(ICGCE), Chennai, India, December, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06823413
  • Tanesh Kumar, Bishwajeet Pandey, Teerath Das, and Md Atiqur Rahman, "SSTL Based Green Image ALU Design on different FPGA", IEEE International conference on Green Computing, Communication and Conservation of Energy(ICGCE), Chennai, India, December, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06823417
  • Tanesh Kumar, Bishwajeet Pandey, Teerath Das and S. M. Mohaiminul Islam, "64 Bit Green ALU Design Using Clock Gating Technique on Ultra Scale FPGA", IEEE International conference on Green Computing, Communication and Conservation of Energy(ICGCE), Chennai, India, December, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6823418
  • Bishwajeet Pandey, and Ekta Walia “Clock Gating Aware Energy Efficient Frame Buffer Design on FPGA”, IEEE International Conference on Communication and Computer Vision (ICCCV), December 2013, Coimbatore, India, http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6906735
  • Md. Atiqur Rahman, Teerath Das, Bishwajeet Pandey, Tanesh Kumar and S. M. Tanvir Siddiquee, "Capacitance and Frequency Scaling Based Energy Efficient Image Inverter Design on FPGA", IEEE International Conference on Communication and Computer Vision (ICCCV), December 2013, Coimbatore, India, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6906736
  • Prabhat Singh, Bishwajeet Pandey, Tanesh Kumar, Teerath Das, “LVCMOS I/O Standard Based Counter Design for Energy Efficient Processor on FPGA”, IEEE International Conference on Communication and Computer Vision (ICCCV), December 2013, Coimbatore, India, http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=6906738
  • Tanesh Kumar, Bishwajeet Pandey, Teerath Das, Md Hashim Minver, "LVDCI I/O Standard Based Green Image ALU Design on Ultra Scale FPGA", IEEE 8th International Conference on Industrial and Information Systems (ICIIS), University of Peradeniya, Kandy, Srilanka, pp. 283 - 288, December 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6731996
  • Shalini Jain, Anupam Shukla, Bishwajeet Pandey, Mayank Kumar, VB Taneja, “Efficient Data Structure Based Smart Card Implementation”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06658037
  • Deepa Singh, Bishwajeet Pandey, Deepak Baghel, Jyotsana Yadav, Manisha Pattanaik, “Clock Gated Low Power Memory Implementation on 40nm FPGA”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September, 2013.http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6658025
  • Deepa Singh, Bishwajeet Pandey, B K Sarkar, and Geetam S Tomar, “Performance Evaluation Of Backoff Method -Effect Of Backoff Factor On Exponential Backoff Algorithm”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6657959
  • Bishwajeet Pandey, Jyotsana Yadav, Jagdish Kumar, RaviKant Kumar “Clock Gating Aware Low Power Global Reset ALU and Implemented On 28nm FPGA”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06658026
  • Jagdish Kumar, Bishwajeet Pandey, Mahua Bhatacharya, “An Efficient Approach to Setup High Performance Network Center in Academia”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06657960
  • Bishwajeet Pandey, Sweety Dabas, Deepa Singh, Rajendra Aaseri “IO Standard Based Green Multiplexer Design and Implementation on FPGA”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06658029
  • Veer Pratap Singh, Vijay Shri Chaurasia, Bishwajeet Pandey, and Jyotsana Yadav, “Power Reduction of ITC’99-b01 Benchmark Circuit Using Clock Gating Techniques”, IEEE International Conference on Computational Intelligence and Communication Networks (CICN), Mathura, India, September, 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06658028
  • Bishwajeet Pandey, Deepa Singh, and Manisha Pattanaik, “IO Standard Based Low Power Design of RAM and Implementation on FPGA”, International Conference on Information Applied Electronics (ICIAE), Colombo, Sri Lanka, 15-16 June, 2013, url: http://www.joace.org/uploadfile/2013/0705/20130705030847941.pdf
  • Bishwajeet Pandey and Manisha Pattanaik, “Clock Gating Aware Low Power ALU Design and Implementation on FPGA”, 2nd International Conference on Network and Computer Science (ICNCS), Singapore, April, 2013, http://www.ijfcc.org/papers/206-S2013.pdf
  • Bishwajeet Pandey and Manisha Pattanaik, “Low Power VLSI Circuit Design with Efficient HDL Coding”, IEEE International Conference on Communication Systems and Network Technologies (CSNT), Gwalior, India, April 2013, url: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6524492&tag=1
  • Bishwajeet Pandey, Mayank Kumar, and Shalini Jain, “Flag and Register Array Based High Performance Instruction Set Architecture of Embedded Processor”, IEEE International Conference on Communication Systems and Network Technologies (CSNT), Gwalior, India, April 2013, http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06524496&tag=1
  • Mahendra Pratap Dev, Deepak Baghel, Bishwajeet Pandey, Manisha Pattanaik, Anupam Shukla, “Clock Gated Low Power Sequential Circuit Design”, IEEE Conference on Information and Communication Technologies(ICT), Kanyakumari, India, April, 2013, url: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6558136
  • Bishwajeet Pandey, and Ravikant Kumar “Low Voltage DCI Based Low Power VLSI Circuit Implementation on FPGA”, IEEE Conference on Information and Communication Technologies(ICT), Kanyakumari, India, April, 2013, pp.128-131, url: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06558076
  • Bishwajeet Pandey, Jyotsana Yadav, Yogesh Singh, Rohit Kumar, Sourabh Patel, “Energy Efficient Design and Implementation of ALU on 40-nm FPGA”, IEEE International Conference on Energy Efficient Technologies for Sustainability-(ICEETs), Kanyakumari, India, pp.45-50, April 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6533355
  • Bishwajeet Pandey, Jyotsana Yadav, Yogesh Singh, Pradip Swarnkar, “Energy Efficiency of Asynchronous and Synchronous VLSI Circuit on 40nm and 90nm FPGA”, IEEE International Conference on Energy Efficient Technologies for Sustainability-(ICEETs), Kanyakumari, India, pp.57-60, April 2013. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6533357
  • Bishwajeet Pandey, Jyotsana Yadav, Nitish Rajoria, Manisha Pattanaik, “Clock Gating Based Energy Efficient ALU Design and Implementation on FPGA”, IEEE International Conference on Energy Efficient Technologies for Sustainability-(ICEETs), Kanyakumari, India, April, 2013, pp.93-97. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06533362
  • Bishwajeet Pandey, Mayank Kumar, Nirmal Robert, Manisha Pattanaik, “Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA”, International Conference on Information Technology and Science (ICITS 2013), Bali, Indonesia, March 16-17, 2013, url: http://www.lnit.org/uploadfile/2013/0506/20130506020243704.pdf
  • Bishwajeet Pandey and Manisha Pattanaik, “Mapping Based Low Power Arithmetic and Logic Unit Design with Efficient HDL Coding”, 5th International Conference on Computer Research and Development (ICCRD), Ho Chi Minh City, Vietnam, February 23-24, 2013 url: http://files.asme.org/Catalog/books/PrintBook/34499.pdf